Design Rule Violations

The Design Rule Violations or often referred to as DRV's are a major challenge in physical design flow or the back end implementation of the current day ASIC/SoC designs with advancements in the technology nodes or the integration of more and more transistors into a chip. Obviously, there are objectives that are highly regarded as priority goals to the likes of timing closure or power or utilization.  As the design stage progresses and after the fixing of priority goals, it becomes a bottleneck for these design rules to be met. 

A rule of thumb to be noted here is to never leave the DRV to be fixed at the last stages of the design cycle. The usual tendency is to fix the DRV's which directly impacts the timing violations on the go and leave the other less harmful violations which have many slack margins to be fixed at the end. But one major shortcoming at the final stages is that we might end up with a more congested database, which limits the DRV fixing.

Before getting into the details of DRV's, let's recollect that there is a library file for the standard cells (or the building blocks) that has the details of the characterizations of these cells. This characterization is usually made into a Look-Up Table (LUT) format. As we are aware, the LUT characterizes the delay of the cells by input transition and output load. The tool will calculate cell delays by interpolating between the input slew and output load given in the LUT. However, as the operating points shift further away from the extreme points in LUT, the result becomes more and more inaccurate as tools predict delays by extrapolating beyond the bound. So beyond this point, the actual silicon delay and the values predicted by the tool differ largely. Adding to this, the delays calculated by distinctive tools differ as each tool uses different algorithms for delay predictions. Hence, it is important to avoid extrapolations by all means. 

To amass this claim, for instance, consider a reg to reg path having hold slack as given:
  • Slack =  T_clk2q + T_data - T_hold
If the net in this path has a DRV, which makes way for inaccurate calculation of slack as the T_clk2q, T_data and T_hold vary.

The major DRV's that are to be addressed are:
  • Max Transition
  • Max Capacitance
  • Max Fanout

Fixing strategies

Max Transition: Max trans violation occurs when the input pin transition of a cell is more than the expected value. Usually fixed by:
      • Up-size the driver cell
      • Reroute the input net in the higher metal layer
      • Load splitting
Max Capacitance: Max cap value is the maximum load value a cell is supposed to drive as output. Reports it whenever this value is exceeded. Fixes:
      • Up-size the driver 
      • Adding buffer in the middle of the long route
      • Load splitting of the violated buffer by inserting a buffer tree.
Max Fanout: The Max fanout of output measures its load driving capability. In other words, it is the greatest number of inputs of gates to which the output can safely connect.



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Static and Dynamic Power Dissipation


In today's world, we need sleeker devices with more capabilities and longer battery life. This can be achieved by packing more components on smaller chips, thus moving to low geometry chip design. However, power dissipation occurs in all the circuits that are currently used, which increases the overall power consumption, making it less suitable for mobile applications which need longer battery life.

The rising demand for portable devices such as mobile phones and even wearable electronic devices for need longer battery life, low power consumption and lesser device weight. Considering this, there seems a need to develop a solution that can make use of low voltage and low power design techniques. The power consumption is also considered as an important criterion in VLSI design along with timing and area. In order to create an ideal solution for this problem, Low Power Design has to be considered as a crucial factor.

Power dissipation has become one of the major problem as it results in heating up of the device which will affects the operation of a chip. There are many kinds of external heat sinks and software based methods are provided with the system, but we have scope to save the power during operation of the chip.

Types of Power Dissipation

The power dissipation is classified in two categories

  1. Static power dissipation
  2. Dynamic power dissipation
Total power dissipation is the sum of the dynamic and static power (leakage power). Dynamic power is the sum of two factors: switching power plus short circuit power. Dynamic power is dissipated only when switching but static power (leakage power) due to leakage current is continuous. 

Total Power = Pswitching + Pshort-circuit + Pleakage

 Static power dissipation

The power dissipation occurs in the form of leakage current when the system is not powered or is in standby mode. In other words, power will be dissipated irrespective of frequency and switching of the system. Leakage power due to leakage current is continuous become more dominant at lower technology nodes. In geometries smaller than 90nm, leakage power has become the dominant consumer of power whereas for larger geometries, switching is the larger contributor.

In circuits, there are several sources of leakage current which cause static power dissipation.

  1. Sub-threshold current
  2. Gate oxide leakage
  3. Diode reverse bias current
  4. Gate induced leakage

Static power (leakage power) is a function of the supply voltage, the switching threshold voltage and the transistor size. 

PLeakage = f (Vdd, Vth, W/L)

Where Vdd = the supply voltage, Vth = the threshold voltage, W = the transistor width and L = the transistor length.

Dynamic power dissipation

There are two reasons for dynamic power dissipation; Switching of the device and Short circuit path from supply to ground. This occurs during operation of the device.

Switching power is dissipated when charging or discharging internal and net capacitances.


Each time the capacitor Cgets charged through the PMOS transistor, its voltage rises from 0 to Vdd and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the high-to-low transition, this capacitor discharged, and the stored energy is dissipated in the NMOS transistor. This way power is dissipated through charging and discharging. This is known as Switching power dissipation. 

Pswitching = a.f.Ceff.Vdd2

Where a = switching activity factor, f = switching frequency, Ceff = the effective capacitance and Vdd = the supply voltage.

Short-circuit power is the power dissipated by an instantaneous short-circuit connection between the supply voltage and the ground at the time the gate switches state. When the input transition time is very high, there will be certain duration of time “t”, for which both the devices (PMOS and NMOS) are turned ON. Now, there is a short circuit path from Vdd to ground.

Short Circuit Path from Vdd to ground

Pshort-circuit = Isc.Vdd.t

Where Isc = the short  circuit current, Vdd = the supply voltage and t = short circuit time.


Click this to get next topic : Techniques to reduce Power Dissipation 

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Introduction to Low Power Design


In today's world, we need sleeker devices with more capabilities and longer battery life. This can be achieved by packing more components on smaller chips, thus moving to low geometry chip design. However, power dissipation occurs in all the circuits that are currently used, which increases the overall power consumption, making it less suitable for mobile applications which need longer battery life.

The rising demand for portable devices such as mobile phones and even wearable electronic devices for need longer battery life, low power consumption and lesser device weight. Considering this, there seems a need to develop a solution that can make use of low voltage and low power design techniques. The power consumption is also considered as an important criterion in VLSI design along with timing and area. In order to create an ideal solution for this problem, Low Power Design has to be considered as a crucial factor.

Power dissipation has become one of the major problem as it results in heating up of the device which will affects the operation of a chip. There are many kinds of external heat sinks and software based methods are provided with the system, but we have scope to save the power during operation of the chip.

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E-Book : VLSI Interview Questions with Answers




VLSI Interview Questions with Answers by [Sony, Sam]You get very carefully chosen 83 of the most important, most likely to be asked questions with illustrated answered, when it comes to interviewing in the field of digital VLSI and ASIC design. Knowing answers to these questions will ensure that you get the job offer from your next interview.
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  4. Divide a clock by 3.
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E-Book : Static Timing Analysis Interview Questions



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VLSI INTERVIEW QUESTION: Static Timing analysis


First of all, I would like to mention that this book can be used by Both Interviewer and Interviewee.

If you are a student/interviewee - This book helps you to crack the Interview or I would say, help you to perform far above your expectation. These questions are asked in several companies (Obviously not all questions in a single interview) by several experts. I am not claiming that "This Is It" but the selection process depends on several other factors but I can assure you that if you have finished this book, you can answer any questions in the interview.
If you are an Interviewer - it will help you to extract more information in less time. It's not recommended to write down the questions which you would ask in the Interview but this book can help to understand what all different questions can be asked related to Static Timing Analysis.




The structure of this book is different from any other book or you can say it's unique in one way. It will give you a feeling of a real-time scenario. Every question has its level of Difficulty, Expected Answer, Explanation (Detail Overview), Follow up Questions, and Objective.


The last section "Follow up Question" is itself a unique concept in the publishing domain. It will guide you on how different questions are linked with each other. Sometimes we prepare a lot but we don't know inter-related questions, it's obvious to miss few of them but when Interviewer asked those questions ( during cross-questioning), we realized that thinking that - Hope I have prepared this one also. :) In short, this portion helps you to prepare all the inter-related questions.
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Note: This Book has 42 Main Questions and 119 Follow Up Questions.

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Sign Off Checks


Layout will be ready after routing stage. Some checks we have to perform soon after the completion of layout to check whether our layout works as designed. These checks are known as Signoff checks.
  1. Physical Verification 
  2. Timing Analysis 
  3. Logical Equivalence Checking (LEC)
Physical Verification

a) Layout versus Schematic (LVS)
DRC verifies whether the given layout satisfies the design rules provided by the fabrication unit. For verifying the functionality, LVS is introduced.
LVS is a crucial check in the physical verification stage. The LVS tool creates a layout netlist, by extracting the geometries. This layout netlist is compared with the schematic netlist of the same stage for verifying whether they are functionally match or not. If the two netlists match, then the LVS reports clean. Else the tool reports the mismatch and the component and location of the mismatch. Some of the LVS errors are:
  • Shorts:-Wires that should not be connected are overlapping.
  • Opens:- Connections are not complete for certain nets.
  • Parameter mismatch:- It checks for parameter mismatches. If the value of particular component is different in layout and the schematic. Then it report as parameter mismatch.
b) Design Rule Check (DRC)
DRC checks determine whether the layout satisfies certain rules specified by the fabrication team. Some of the rules are spacing between metals layers, minimum width rules, via rules etc. An input to the design rule tool is a design rule file.
Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different metal layers with respect to different fabrication process. If we give physical connection to the components without considering the DRC rules, then it will lead to failure of functionality of chip. So the DRC should be clean before giving to fabrication.
Common DRC rules are:
  • Interior
  • Exterior
  • Enclosure
  • Extension
Logical Equivalence Checking
Logical Equivalence check (LEC) will compare the golden netlist with the revised netlist. Golden Netlist or pre-layout netlist is nothing but the synthesis netlist and the revised netlist or post-layout netlist is what we get after PnR flow. The noticeable difference between the pre-layout-netlist and post-layout-netlist is the inclusion of clock tree buffers and other normal buffers at the time of optimization are in the post-layout-netlist.
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Static Timing Analysis

Definition
Static Timing Analysis (STA) is a technique of verifying our circuit meets timing constraints or not without having to simulate. The basic timing violations are setup violation and hold violation.

Difference between Static Timing Analysis (STA) and Dynamic Timing Analysis (DTA)

Static Timing Analysis
  • Less Accurate (Formula based analysis)
  • Faster when compared to DTA
  • Checks only the synchronous part of a design not for asynchronous
  • Checks for timing only
Dynamic Timing Analysis
  • Very Accurate (simulation based analysis)
  • Slower when compared to STA
  • Checks synchronous part as well as asynchronous part of a design
  • Checks for both timing as well as functionality
Timing Exceptions
These are nothing but constraints which do not follow the default when doing the timing analysis. The different types of timing exceptions are,
  • False Path : If the path does not affect the output and does not contribute to the delay of the circuit then that path is called as False path.
  • Multi-cycle Path : Multi-cycle paths are the paths that require more than one clock cycle. Therefore they require multi-cycle setup and hold time calculations.
  • Max/Min Delay :This path must match a delay constraint that matches a specific value. It is not an integer like multi-cycle path. For eg: delay from one point to another max: 1.78ns and min: 1.92ns.
Inputs required for STA
Following are the inputs needed by Prime Time (STA tool)
  • Gate level netlist
  • SPEF
  • SDC
  • SDF
  • Library files 
Outputs from STA 
  • Timing Report
Basic definitions 
  • Clock : Clock is a signal that oscillates between a high and a low state. Clock controls timing in the design.
  • Setup Time : Setup time is the minimum amount of time before the capture clock edge so that the data must be held steady for the proper latch by the storage device.
  • Hold Time : Hold time is the minimum amount of time after the clock edge for ensuring the data captured is properly captured or not.
  • Required Time : Required time is defined as the time required to arrive at certain point.
  • Arrival Time : Arrival time is defined as the time at which a signal to arrive at a point.
  • Slack : Slack is the difference between the required time and the arrival time of a signal.
Setup slack = Required time - Arrival time
Hold slack = Arrival time - Required time
  • Latency : Clock latency is defined as the amount of time taken by the clock signal in travelling from its source to the sinks. Source latency is the delay from the clock origin point to the clock definition point. Network latency is the delay from clock definition point to the clock pin of the sequential elements.
  • Jitter : Jitter is the amount of cycle to cycle variation that can occur in a clock period.
  • Clock Skew : The common sourced clock signal arrives at different components at different times. The difference in arrival times of the clock signal at any two flip-flops which are interacting with one another.
  • Positive Skew : When the source flip-flop is clocked first than the destination flip-flop, then it is positive skew. Positive skew is good for fixing setup violation.
  • Negative Skew : When the destination flip-flop is clocked first than the source flip-flop, then it is negative skew. Negative skew is good for fixing hold violation.
Advanced STA article will be published soon....

     


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Physical Design Sanity Checks


The main intention of sanity checks in Physical Design is that they are mainly done for checking the design for further acceptance at each stages of the physical implementation. It qualifies the netlist in terms of timing, checks the issues related to library files, constraints files etc.

Following are the sanity checks carried out in physical design flow:
  • check_library
  • check_timing
  • check_design
  • check_legality
  • report_timing
  • report_qor
  • report_constraint
check_library: It performs consistency checks between logical and physical libraries. That means each cells that are described in the netlist has its corresponding physical, timing and logical information defined in the libraries.

check_timing: PNR tool won't optimize the paths which are not constrained. So we have to check any unconstrained paths are exist in the design. The check_timing command will report the unconstrained paths. If there are any unconstrained paths in the design, run the report_timing command to verify whether the unconstrained paths are false paths.

check_design: This check is to report problems like undriven input ports, unloaded output ports, nets/ports with multiple drivers, unloaded nets, pins mismatch, cells or instances with out I/O pins/ports etc.

check_legality: It reports violations regarding to cell overlaps and orientation.


report_timing: The report_timing command provides a report of timing information for the current design. By default, the report_timing command reports the single worst setup path in each clock group.

report_qor: It reports the statistics/QoR of the current design includes its timing information, cell count, details like combinational and sequential cells, total area of the current design. This will also reports any DRV s present.

report_constraint:  It reports the following parameters in the current design such as WNS, total negative slacks, DRC violations etc. The report includes whether the constraints are violated or not, by how much it is violated and the worst violating object.

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Antenna Effect

Definition
During the fabrication of MOS integrated circuits, especially at the time of plasma etching, there will be a chance of collecting more charges at the gate and causes damage to the gate oxide layer since it is very thin. This condition is known as Antenna effect.

Antenna Violation 
The ratio of the gate area to the gate oxide area is known as Antenna ratio. Because the area/size of the conductor (gate area) will decide the magnitude of the charge collection. When this ratio exceeds a value specified in a Process Design Kit (PDK) , will leads to Antenna violation.

Click here to go to Process Design Kit (wikipedia).

Solutions for Antenna Violation
  • Metal jumpers : Break signal wires and route to upper metal layers by jumpers. Jumper insertion breaks the long wire which is connected gate and route to upper metal layer. So it becomes short and less capable of collecting charge. If the antenna violation happens at a metal layer, always use higher metal layers as metal jumper since all the lower layers are already fabricated at that moment.
  • Diode insertion : Connect reverse biased diodes near gate input where violation occurs on a net provides a discharge path to the substrate which saves the gate of the transistor. Adding diode increases the area and also the capacitance which leads to increase in delay. 



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