Clock Tree Synthesis (CTS)

  • Clock Tree Synthesis (CTS) is a process which make sure that the clock gets distributed evenly to all sequential elements in a design.
  • CTS is the process of insertion of buffers or inverters along the clock paths of ASIC design in order to achieve minimum skew or balanced skew.
  • In ICs, clock consumes around half of the total power consumption. Here clock gating technique helps to reduce power consumption by the clocks.
Goals of CTS
  • To meet clock tree design rule constraints such as maximum transition, maximum load capacitance and maximum fanout.
  • To meet clock tree targets such as minimum skew and minimum insertion delay.
Checklist before CTS
  • Placement is completed and optimized-
  • Power & Ground (PG) nets are prerouted
  • Estimated congestion - Acceptable
  • Estimated Max trans/Cap - No violations
  • High Fan-out Nets are synthesized with buffers (clocks are not buffered still)
Checklist after CTS
  • Skew report
  • Clock tree report
  • Timing reports for setup and hold
  • Power and area report
After placement stage, all the cells including macros and standard cells are placed. But the clock is still ideal. We only optimise the data paths at placement stage with buffer insertion and cell sizing, but no change is done in the clock net.

Just look into the above figure. Here the clock port connects all the synchronous elements in the design. The fanout of the particular port driver is too high and also the clock is not reaching all the flops at a time. The clock network delays are different. So the skew value is very high, which is not recommended in a design. That's why CTS is performed to balance the clock net by adding buffers and minimise the skew as much as possible (ideally the skew value is zero). After the clock tree synthesis, the clock net is buffered and the NDR rule is also applied as shown in the below figure.

Difference between HFNS and CTS?
HFNS (High Fanout Net Synthesis) used in placement stage which uses buffers and inverters of relaxed rise and fall times. But in CTS (Clock Tree Synthesis), buffers and inverters of equal rise and fall times are used. NDR rules are also used for clock tree routing.

Note : The reason why the clock is defined as ideal in placement stage is, if we don't define clock as ideal, the HFNS will insert buffers, inverters and other optimisations in clock net also. But the clock nets need buffers and inverters of equal rise and fall times, not the normal buffers used by HFNS.

Difference between Clock buffers and Normal buffers
  • Clock buffers have equal rise and fall time.
  • Normal buffers have unequal rise and fall time.
  • Clock buffers are usually designed such that an input signal with 50% duty cycle produces an output signal with 50% duty cycle.
Note : Buffers have unequal rise and fall times is because of the difference in PMOS and NMOS resistances. Normally the resistance of the PMOS is two times more than that of NMOS. So the time taken for charging the load capacitor (rise time) through PMOS is more than the discharging time through NMOS (fall time). For designing clock buffers we should make both the resistances of PMOS and NMOS equal. We have to increase the width of PMOS such that its resistance become equal to NMOS resistance. These clock buffers are specially designed for clock path. The main disadvantage of clock buffer is its big size because of increased width of PMOS. So these buffers will lead to increase the chip area.

Non-Default Clock Routing

Non-Default Routing (NDR) rules are double spacing, double width and shielding. These are used to applied on the clock nets to make it less sensitive to crosstalk and electromigration effects.

Free CTS Test: Clock Tree Synthesis Interview Questions



  1. Best blog in vlsi physical design. Great job..

  2. clear explanation. Great job...

  3. Why do we need equal rise and fall time for clock buffers and inverters? Will an unequal rise and fall time not work at all?

    1. Rise and fall times of clock buffers are nearly equal. The reason behind this is that if the clock buffers are not balanced, there will be duty cycle distortion in the clock tree, which can lead to pulse width violation.

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