Floor Planning

Floorplanning is the most important stage in Physical Design. It is a factor that directly affects the following in a design:
  • Congestion and routing issues.
  • IR drop
  • Timing etc.
In floorplanning, we define the size and shape of your chip or block, place the IO pins/pads, macros and blockages in the core or chip area in order to effectively find the routing space between them. At floorplanning, we reserve space for the placement of standard cells.

Quality of your chip is determined by your Floorplan. A well organized floorplan results in more efficient utilization of the core area thereby aiding the placement of the standard cells without causing issues related to congestion, timing, signal integrity etc.

If the flooplan is bad, it affects the area, power, reliability of the chip and requires more efforts for closure and it can increase overall IC cost also. It can create all kind of issues in the design like congestion, timing, noise, ir, routing issues etc.

Floorplan Steps
  • Size and shape of the block
  • Voltage area creation (Power domains)
  • IO placement
  • Creating Standard cell rows
  • Macro-placement
  • Adding routing & placement blockages (as required)
  • Adding power switches (Daisy chain)
  • Creating Power Mesh
  • Adding physical only cells (Tap cells, boundary cells/End Cap cells/Corner cells etc)
  • Placing & qualifying pushdown cells
  • Creating bounds / plan groups / density screens
  • The output of the floorplan is a DEF contains die/core area, placed macro information, blockage information (soft/hard/partial blockage), placed IO pin/pad information.
 Sanity checks before Floorplan:
Types of Floorplan techniques in full chip design:
  • Abutted floorplan: Channel less placement of blocks.
  • Non-abutted: Channel based placement of blocks for block interconnections.
  • Partially abutted: Partial abutment of blocks with channels in certain areas.

Floorplan control parameters:
In PnR tool, floorplanning can be controlled by various parameters  They are,
  • Aspect Ratio: It is defined as the width to height ratio of the chip. The width and height corresponds to the vertical and horizontal routing resources available respectively. If AR>1, then the block will be of rectangular shape with width>height, as routing resources in the vertical direction is more. If AR<1, then also the block will be rectangular shape with width<height, as routing resources in the horizontal direction is more. The block shape will be square if AR=1.  
AR= No. of horizontal routing resources/ No. of vertical routing resources
  • Core Utilization: It is the percentage of area that is used for cell placement. It is calculated as the ratio of total cell area (ie. Standard cell area + Macro cell area) to the core area. For instance, if we are taking utilization to be 0.7, then it means that 70% of the area is used for cell placement and the rest 30% is used for routing. 
Core Utilization= (Standard Cell Area+ Macro Area) / Total Core Area

Floorplanning Guidelines:
  • Using Flyline analysis, place macros which are connected to each other closer
  • Place the macros near to the IO pins, if it connect to IO pins.
  • Place macros near the boundary of the block.
  • It is recommended to avoid criss cross placement of macros, in order to save the routing resources, congestion as well as to avoid other issues related to timing, placement of standard cells etc.
  • Provide a halo space around all sides of the macros.
  • Provide proper blockages as per the requirement. The different types of blockages are given below:
Types of Blockages
  • Soft Blockage: It restricts placement of standard cells inside the blockage area and allows buffers to be placed at the time of optimization to meet timing.
  • Hard Blockage: Both standard cells and buffers are prohibited inside hard blockage area.
  • Partial Blockage: The designer can customize the amount of space to inside the blockage area. If a value of 50% is given, 50% area is blocked for any placement and the rest is available for optimization.
Spacing between macros: A considerable spacing must be there between macros for pin sides and a minimal spacing is given for non- pin sides of macros. The spacing between macros with pin sides is found out by the following relation:
Channel spacing between macros = (No. of pins x pitch)/(Available layers/Total layers).
The pitch here, corresponds to the pitch of the top layer of pins among the two macros. For instance, if there are two macros namely A and B, in which the pins of A is in Metal 2 and that of B is in Metal 4, then the pitch of Metal 4 is taken into account.
  • After the placement of macros, set all of them to be fixed, so that later, the macros will not move from the placed location.
  • Reduce open fields to the minimum, except for reserved routing resources. This can be reduced with trying different Aspect Ratios if possible.
  • Budget space for Power network as per the requirement. If not, it may lead to routing congestion in later stages.
  • Then the next step is Power planning
How to Qualify Floorplan:
  • P/G connections to all the macros and pre- placed cells are synthesized.
  • All the macros are placed at the boundary in order to reduce effect of IR drop.
  • All unwanted blockages(placement and routing) is removed.
  • Proper channel spacing is there between macros and also between macro to boundary in order to insert buffers for optimization and also minimize congestion issues. 
Power Planning
  • Power Planning is a step done along with floorplanning inorder to distribute power with proper power drop analysis across the design so that entire design is getting power uniformly. 
  • It is also called Pre-routing as the Power Network Synthesis (PNS) is done before actual signal routing and clock routing. 
  • First estimation of power dissipation of the design is carried out by calculation or using power analysis tools. 
  • Based upon this estimation the width of the power ring and width and number of power straps are calculated.

    To meet the IR drop budget (In failing so, the standard cells, macros etc. won’t be getting the required power supply).

    • Power mesh is synthesised with IR Drop within the estimated margin (usually less than 5%).
    • Floorplan with synthesised power mesh
    • If the IR drop budget is met.
    • Power DRC’s, i.e, check for any floating pins.
    • Placement legality is met.
    The power network contains the following
    • Power Ring : Carries VDD and VSS around the core.
    • Power Strap : Carries VDD and VSS across the core.
    • Power Rails : Connects VDD and VSS to the standard cells.



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