Gate Level Netlist

Gate Level Netlist
  • Synthesis is the process of converting RTL to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity).
  • Netlist contains the information regarding logical connectivity of all standard cells and macros.
  • It provides the details of nets and its connectivity.
  • The common netlist file formats are .v or .vg and .ddc files.
    • .v: contains the net connectivity information between cells and macros, gate level descriptions of the cells.
    • .ddc: it contains both the net connectivity info as well as the scan chain info and gate level descriptions of the cells.
  • Physical design will convert the gate level netlist to complete physical geometric representation. The file produced at the output of the layout is the GDSII (GDS2) file or oas which is the file used by the foundry to fabricate the silicon. The layout should be done according the silicon foundry design rules.
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