Logical Libraries
- It provides the timing and functionality information for all the standard cells (AND gate, OR gate, flip flops etc.)
- Provides the timing informations for hard macros like IP, ROM, RAM etc.
- It contains drive/ load design rules such as:
- Max fanout
- Max transition
- Max/min capacitance
- Setup time, hold time, recovery and removal time, delays info of the cells are available.
- Cell delays are represented in terms of look up tables, and is a function of input transition and output load.
Timing Model
Tools need a timing model in the form of a .lib file. Synopsys ICC takes a .db file, which is generated from a .lib. This liberty format file will have timing numbers for the various arcs in a cell, generally in a look up model. This .libs may have cell power information also.
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