Placement is the process of placing standard cells in the rows created at floor planning stage.

Steps in Placement stage
  • Pre-placement
  • Coarse placement (initial placement)
  • Legalization
  • High Fanout Net Synthesis (HFNS)
  • Placement optimizations
  • Area Recovery
  • Scan chain reordering
In this step, the following things are implemented, 
  • Adding Antenna diodes and buffers on block level ports.
  • Adding Tap Cells for avoiding latch-up problem.
  • Insertion of Spare cells.
  • If design wants, adding some special cells also.
  • Insertion of de-coupling capacitors (rare in recent designs).

Coarse Placement 
During coarse placement, the PnR tool will determine an approximate location for each cell according to the timing and congestion. In fact the macros act as placement blockages for standard cells in this stage. Coarse placement is mainly performing for initial timing and congestion analysis.

During legalization, the tool will move the cells to legal locations for avoiding overlap between cells. These changes in the cell location will change the length of signal net leads to new timing violations. These can be fixed by incremental optimization.

High Fanout Net Synthesis (HFNS)
  • High Fanout Net is the net which drives more number of loads. There is a limit for maximum number of loads per net. The nets which cross more than these limit are known as High Fanout Nets.
  • The process of buffering the high fanout nets is known as High Fanout Net Synthesis (HFNS).
  • Clock nets, reset, scan, enable nets are generally considered as High Fanout Nets. HFNS is performed at the placement stage. Since clock nets are considered ideal at placement stage, HFNS is not performed on clock nets even though they are High Fanout Nets. Also it is not performed on don't touch attribute nets.
  • We synthesize clocks in the next stage ie. CTS stage. Make sure to define clocks as ideal in the placement stage, otherwise HFNS will be done on the clock. Clock constraints like skew or clock buffers are not used here and effectively the clock tree will messed up.
Placement Optimizations
Congestion: Congestion occurs if the number of routing tracks available for routing are less than the required number of routing tracks. Following techniques are used for reducing congestion.
  • Placement Blockages : Inorder to avoid placement in some areas, placement blockages are used. Different types of placement blockages are soft blockage: It restricts placement of standard cells inside the blockage area but allows buffers to be placed at the time of optimization to meet timing. Hard blockage: It prevents cells from being placed in this blockage area. Both standard cells as well as buffers are prohibited inside hard blockage area. Partial blockage: The designer can customize the amount of space to inside the blockage area.
  • Macro Padding : Macro padding or halos (keep-out margin) around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pins outs of the macros, thereby giving enough space for the macro pin connections to standard cells.
  • Cell Padding : Cell padding refers to placement clearance applied to standard cells in PnR tools. This is typically done to ease placement congestion to reserve some space for future use down the flow. For example typically people apply cell padding to the buffers/inverters used to build clock tree, so that space is reserved to insert decap cells near them after clock tree synthesis.
  • Maximum Utilisation Constraint : Some tools will specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.
Scan Chain Re-ordering 
It is the process of reconnecting the scan chains in a design to optimize for routing by re-ordering the scan connection which improves congestion as well as timing. At the time of placement the optimization may take the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion. Since logic synthesis arbitrarily connects the scan chain, we need to perform scan reorder after placement so that the scan chain routing will be optimal.

How to qualify placement
  • Check legalization for any overlapping.
  • Check PG connections for all the cells.
  • Check global congestion, pin density and cell density.
  • Check whether all don't touch cells and nets are preserved.
  • Check for setup time violation.


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