Timing Constraints

Timing Constraints

• Timing constraints in a design are saved in a common format which is supported by most of the tools and the format is known as SDC (Synopsys Design Constraints). This constraint file is saved with an .sdc extension. 
• The SDC files contains constraints related to timing of the design.
• Timing constraints are required for communicating timing intentions of design to the tool.
• The .sdc file must be same as the one used for synthesizing the netlist.
• The constraints include the following:
• Clock definition
• Generated clock info
• Input/ Output delay
• Max/Min delay
• Timing exceptions such as false path, multicycle paths etc.
• Clock uncertainty, transition, latency etc.