Signal Integrity

Signal integrity is the ability of an electrical signal to carry information reliably and resist the effects of high-frequency electromagnetic interference from nearby signals.
Following are the some of the signal integrity effects might occur in ASIC design.
  • Crosstalk
  • Electro migration
  • Antenna Effect

  • Due to the influence of cross coupling capacitance, switching of the signal from one net (aggressor) to the neighboring net (victim). This is known as crosstalk.
  • During the transition on adjacent signal (aggressor net) causes a noise bump/glitch on constant signal (victim net). This noise is called as crosstalk noise.
Solution for crosstalk
  • Double Spacing : Increase the spacing between the aggressor net and victim net, so that the cross coupling capacitance decreases as spacing increases and thereby reduces the effect of crosstalk.
  • Shielding : Placing a ground net (Vss) in between the aggressor net and victim net so that the voltage will discharge through this and save from crosstalk issue.
  • Buffer Insertion : Insertion of buffers will boost the strength of the victim net and thereby reduce the effect of crosstalk.
  • Due to high current density, the electrons in the metal moved with high acceleration. And these electrons transfer their momentum to other atoms and the atoms get displaced from their original position and might create voids and hillocks.
  • Hillocks will create shorts and voids will create opens between metal layers.

Fig (a): Void (Open)                   Fig (b): Hillock (Short)

Solution for Electromigration
  • Increase the width of the wire
  • Insertion of Buffers
  • Upsizing the driver cell
  • Switch the net into higher metal layer
Antenna Effect
During the fabrication of MOS integrated circuits, especially at the time of plasma etching, there will be a chance of collecting more charges at the gate and causes damage to the gate oxide layer since it is very thin. This condition is known as Antenna effect.

Antenna Violation 
The ratio of the gate area to the gate oxide area is known as Antenna ratio. Because the area/size of the conductor (gate area) will decide the magnitude of the charge collection. When this ratio exceeds a value specified in a Process Design Kit (PDK) , will leads to Antenna violation.

Click here to go to Process Design Kit (wikipedia).

Solutions for Antenna Violation
  • Metal jumpers : Break signal wires and route to upper metal layers by jumpers. Jumper insertion breaks the long wire which is connected gate and route to upper metal layer. So it becomes short and less capable of collecting charge. If the antenna violation happens at a metal layer, always use higher metal layers as metal jumper since all the lower layers are already fabricated at that moment.
  • Diode insertion : Connect reverse biased diodes near gate input where violation occurs on a net provides a discharge path to the substrate which saves the gate of the transistor. Adding diode increases the area and also the capacitance which leads to increase in delay. 



    1. Very useful blog thank you very much

    2. Increasing the Drive strength will worsen the EM