Static Timing Analysis

Definition
Static Timing Analysis (STA) is a technique of verifying our circuit meets timing constraints or not without having to simulate. The basic timing violations are setup violation and hold violation.

Difference between Static Timing Analysis (STA) and Dynamic Timing Analysis (DTA)

Static Timing Analysis

• Less Accurate (Formula based analysis)
• Faster when compared to DTA
• Checks only the synchronous part of a design not for asynchronous
• Checks for timing only

Dynamic Timing Analysis

• Very Accurate (simulation based analysis)
• Slower when compared to STA
• Checks synchronous part as well as asynchronous part of a design
• Checks for both timing as well as functionality

Timing Exceptions
These are nothing but constraints which do not follow the default when doing the timing analysis. The different types of timing exceptions are,

• False Path : If the path does not affect the output and does not contribute to the delay of the circuit then that path is called as False path.
• Multi-cycle Path : Multi-cycle paths are the paths that require more than one clock cycle. Therefore they require multi-cycle setup and hold time calculations.
• Max/Min Delay :This path must match a delay constraint that matches a specific value. It is not an integer like multi-cycle path. For eg: delay from one point to another max: 1.78ns and min: 1.92ns.

Inputs required for STA
Following are the inputs needed by Prime Time (STA tool)

• Gate level netlist
• SPEF
• SDC
• SDF
• Library files 

Outputs from STA 

• Timing Report

Basic definitions 

• Clock : Clock is a signal that oscillates between a high and a low state. Clock controls timing in the design.
• Setup Time : Setup time is the minimum amount of time before the capture clock edge so that the data must be held steady for the proper latch by the storage device.
• Hold Time : Hold time is the minimum amount of time after the clock edge for ensuring the data captured is properly captured or not.
• Required Time : Required time is defined as the time required to arrive at certain point.
• Arrival Time : Arrival time is defined as the time at which a signal to arrive at a point.
• Slack : Slack is the difference between the required time and the arrival time of a signal.

Setup slack = Required time - Arrival time

Hold slack = Arrival time - Required time

• Latency : Clock latency is defined as the amount of time taken by the clock signal in travelling from its source to the sinks. Source latency is the delay from the clock origin point to the clock definition point. Network latency is the delay from clock definition point to the clock pin of the sequential elements.
• Jitter : Jitter is the amount of cycle to cycle variation that can occur in a clock period.
• Clock Skew : The common sourced clock signal arrives at different components at different times. The difference in arrival times of the clock signal at any two flip-flops which are interacting with one another.
• Positive Skew : When the source flip-flop is clocked first than the destination flip-flop, then it is positive skew. Positive skew is good for fixing setup violation.
• Negative Skew : When the destination flip-flop is clocked first than the source flip-flop, then it is negative skew. Negative skew is good for fixing hold violation.

Advanced STA article will be published soon....