Sign Off Checks


Layout will be ready after routing stage. Some checks we have to perform soon after the completion of layout to check whether our layout works as designed. These checks are known as Signoff checks.
  1. Physical Verification 
  2. Timing Analysis 
  3. Logical Equivalence Checking (LEC)
Physical Verification

a) Layout versus Schematic (LVS)
DRC verifies whether the given layout satisfies the design rules provided by the fabrication unit. For verifying the functionality, LVS is introduced.
LVS is a crucial check in the physical verification stage. The LVS tool creates a layout netlist, by extracting the geometries. This layout netlist is compared with the schematic netlist of the same stage for verifying whether they are functionally match or not. If the two netlists match, then the LVS reports clean. Else the tool reports the mismatch and the component and location of the mismatch. Some of the LVS errors are:
  • Shorts:-Wires that should not be connected are overlapping.
  • Opens:- Connections are not complete for certain nets.
  • Parameter mismatch:- It checks for parameter mismatches. If the value of particular component is different in layout and the schematic. Then it report as parameter mismatch.
b) Design Rule Check (DRC)
DRC checks determine whether the layout satisfies certain rules specified by the fabrication team. Some of the rules are spacing between metals layers, minimum width rules, via rules etc. An input to the design rule tool is a design rule file.
Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different metal layers with respect to different fabrication process. If we give physical connection to the components without considering the DRC rules, then it will lead to failure of functionality of chip. So the DRC should be clean before giving to fabrication.
Common DRC rules are:
  • Interior
  • Exterior
  • Enclosure
  • Extension
Logical Equivalence Checking
Logical Equivalence check (LEC) will compare the golden netlist with the revised netlist. Golden Netlist or pre-layout netlist is nothing but the synthesis netlist and the revised netlist or post-layout netlist is what we get after PnR flow. The noticeable difference between the pre-layout-netlist and post-layout-netlist is the inclusion of clock tree buffers and other normal buffers at the time of optimization are in the post-layout-netlist.
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