Design Rule Violations

The Design Rule Violations or often referred to as DRV's are a major challenge in physical design flow or the back end implementation of the current day ASIC/SoC designs with advancements in the technology nodes or the integration of more and more transistors into a chip. Obviously, there are objectives that are highly regarded as priority goals to the likes of timing closure or power or utilization.  As the design stage progresses and after the fixing of priority goals, it becomes a bottleneck for these design rules to be met. 

A rule of thumb to be noted here is to never leave the DRV to be fixed at the last stages of the design cycle. The usual tendency is to fix the DRV's which directly impacts the timing violations on the go and leave the other less harmful violations which have many slack margins to be fixed at the end. But one major shortcoming at the final stages is that we might end up with a more congested database, which limits the DRV fixing.

Before getting into the details of DRV's, let's recollect that there is a library file for the standard cells (or the building blocks) that has the details of the characterizations of these cells. This characterization is usually made into a Look-Up Table (LUT) format. As we are aware, the LUT characterizes the delay of the cells by input transition and output load. The tool will calculate cell delays by interpolating between the input slew and output load given in the LUT. However, as the operating points shift further away from the extreme points in LUT, the result becomes more and more inaccurate as tools predict delays by extrapolating beyond the bound. So beyond this point, the actual silicon delay and the values predicted by the tool differ largely. Adding to this, the delays calculated by distinctive tools differ as each tool uses different algorithms for delay predictions. Hence, it is important to avoid extrapolations by all means. 

To amass this claim, for instance, consider a reg to reg path having hold slack as given:
  • Slack =  T_clk2q + T_data - T_hold
If the net in this path has a DRV, which makes way for inaccurate calculation of slack as the T_clk2q, T_data and T_hold vary.

The major DRV's that are to be addressed are:
  • Max Transition
  • Max Capacitance
  • Max Fanout

Fixing strategies

Max Transition: Max trans violation occurs when the input pin transition of a cell is more than the expected value. Usually fixed by:
      • Up-size the driver cell
      • Reroute the input net in the higher metal layer
      • Adding buffer in the middle if violation is on a long route
Max Capacitance: Max cap value is the maximum load value a cell is supposed to drive as output. Reports it whenever this value is exceeded. Fixes:
      • Up-size the driver 
      • Load splitting of the violated buffer by inserting a buffer tree.
Max Fanout: The Max fanout of output measures its load driving capability. In other words, it is the greatest number of inputs of gates to which the output can safely connect.


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