Floorplanning Test Series 1


  1. What is Floor planning?
  2. How can you say a floor plan is good?
  3. Is timing information mandatory for floor planning?
  4. What are the inputs for floor planning stage?
  5. What are the outputs from floor planning?
  6. What are the floor planning control parameters?
  7. Differentiate Static and Dynamic power? What are the different techniques to save static and dynamic power?
  8. What do you mean by Aspect ratio?
  9. What is Sanity check?
  10. What is cell delay?
  11. What is net delay?
  12. What are the difference between standard cell and macro?
  13. Do static and dynamic power have any relation with power supply?
  14. What is core utilization?
  15. What is total chip utilization?
  16. What is Pre-routing? Why do you need to do it before placement?
  17. What is core limited and pad limited design?
  18. Can macro be placed between core and die boundary or in I/O pad?
  19. How is macro placement done in floor planning? What are the guidelines for macro placement?
  20. What is placement blockage? What are the different types of placement blockages?
  21. What is Halo? How it is useful?
  22. Can we rotate the macro in lower technologies?
  23. What do you mean by Flylines? How it is useful in floorplanning?
  24. What is core utilization percentage?
  25. What are the datas getting from synthesis team? How do you validate them?
  26. What is mean by wire bond and flip chip?
  27. What is the need for sanity checks?
  28. Can area recovery be done by downsizing the cells at path with positive slack?
  29. How to reduce congestion?
  30. What are the inputs requred for floor planning? Explain each?
  31. What is Power planning?
  32. Why do we use alternate routing approach HVH /VHV (Horizontal-Vertical-Horizontal)/(Vertical-Horizontal-Vertical)?
  33. What is the main reason to use flip chip over wire bond package?
  34. How to find out the minimum spacing between two macros?
  35. What are the steps to be taken care while doing floor planning?
  36. Why power stripes routed in the top metal layers?
  37. What would you do in order to not use certain cells from the library?

No comments:

Post a Comment