Clock Tree Synthesis Interview Questions

  1. What is CTS?
  2. What are the goals of CTS?
  3. Which metal layer do you prefer for clock routing and why?
  4. How do you optimize skew/insertion delays in CTS?
  5. What are the effects of metastability?
  6. What are the pros and cons of LVT and HVT cells?
  7. How do you set inter clock uncertainty?
  8. What are the difference in clock constraints from pre CTS to post CTS?
  9. How will you fix setup violation?
  10. How will you fix hold violation?
  11. How do you minimize clock skew or balance the clock tree?
  12. Draw the timing diagrams to represent the propagation delay, setup, hold, recovery, removal and minimum pulse width?
  13. How does the jitter affect the setup and hold paths?
  14. Is the clock gating used for power or timing?
  15. What are the difference between Clock buffers and Normal buffers?
  16. What is useful skew?
  17. What is the difference between clock tree synthesis and high fanout net synthesis?


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  2. 1. CTS is a process of distributing clock signal from the clock definition point to all the sequential circuits in the design.

    *Minimizing skew and latency
    *Meeting the clock tree drcs(max cap,max tran,max fanout)

    3. Top metal layer immidiatly after the layer which is used for power grid routing.
    Because top metal layers will have less resistivity hence less IR drop.

  3. The tree is synthesized using a variety of buffers in such a way that very few paths share a route back to the clock root.