Q36> Power routes generally conduct a lot of current. In order to reduce effect of IR drop, we need to make these routes less resistive. Top metal layers are thicker and offer lesser resistance. This helps to reduce IR drop.
Q35> Following are the steps to be taken care while doing floor planning. 1. Die Size Estimation 2. Pin/pad location 3. Hard macro placement 4. Placement and routing 5. Location and area of the soft macros and its pin locations 6. Number of power pads and its location
the pitch varies for different metal layers. which metal layer pitch we need to consider? for e.g: in layerstack with 8 metal layers with 5 1x, 2 2x and 1 ultra thick metal, width and space is different for each of these categories.
Q33> Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs. Following are the Process Advantages of Flip-Chip Design 1. Device Speed 2. Power and Ground Distribution 3. I/O Density with Area Array 4. Package Size /Form Factor 5. Low Stress over active Area 6. Reliability
Q28> Yes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting unwanted buffers will also help in area recovery
Q27> The main reason for using Sanity check is used to checking/qualifying the design for further acceptance at each stages of the physical implementation. It qualifies the netlist in terms of timing, checks the issues related to library files, constraints files etc. Following are the sanity checks carried out in physical design flow: (a) check_library: It performs consistency checks between logical and physical libraries. (b) check_timing: This is to check any unconstrained paths present in the design. check whether the pins/ports has it's corresponding I/O delays and also checks for the clock definition exists for all flop pins. (c) check_design: This check is to report problems like undriven input ports, unloaded output ports, nets/ports with multiple drivers, unloaded nets, pins mismatch, cells or instances with out I/O pins/ports etc.
Q26> Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs.
Q24> Core utilization = (standard cell area+ macro cells area)/ total core area A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20% is left free for routing.
Q23> Flylines means check net connections from macro to macro and macro to standard cells. If there is more connection from macro to macro, place those macros nearer to each other preferably nearer to core boundaries.
Q22> In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation.
Q21> Halo (Keep-out Region) is a region around boundary of fixed macro in desig in which no other macro or std cells can be placed. Placement of cells out of such region avoids congestion.
Q20> In order to avoid placement in some areas, they are used. There are 3 types of Placement blockages (a) Soft Blockage: allows only buffer & inverters to optimizes/ meet the timing. Used for Timing purpose only. Advantages is that Area is less, Timing is ease & less transition time. (b) Hard Blockage: Won't allow any cell. Used for Routing purpose only. Advantages is used to avoid congestion. Disadvatages is Area is wastage. (c) Partial Blockage: Some % of all celss can be used. No of available tracks can be increased uisng this. Advantages is to meet timing, routing easy & less IR drop.
Q19> Macro placement can be done using Macro guidelines. 1. Based on Flylines analysis (connections) between macros. 2. Macro should be near to core boundaries. 3. Communicating macros should be placed nearer. 4. Macro cell pin direction should be towards std cell direction. 5. Two Macros in between, we can placed/add soft bloackages 6. MAcros alignment should be follow 7. Criss Cross connection is not allowed. 8. Notches( edges) is avoided, 9. Orientation is not allowed.
Q18> Yes. Core is defined as the inner block, which contains the standard cells and macros. There is another outer block which covers the inner block. The I/O pins are placed on the outer block.
Q17> 1. Pad Limited Design : A design is called Pad limited design when there are large number of pad cells determining the die size 2. Core Limited Design : A design is called Core limited design when the large number of standard cells and macros determine the die size.
Q16> Prerouting means routing of PG nets. Power Planning also called Pre-routing as the Power Network Synthesis (PNS) is done before actual signal (net) routing and clock routing. For Area optimization, pre-routing is need to do it before placement(Flip Chip Concept)
Q15> Total utilization T(F) of floorplan F is derived using the following equation T(F) = (A(m) + A(p) + A(s) ) / A where A(m) = Area occupied by macros, A(p) = Area occupied by Pads/ Pad fillers A(s) = Area occupied by Standard Cells
Q14> Core Utilization = (Stdcell area + Macro Cell Area)/ ( Total Core Area)
Q13> Yes. Static Power: The charge power consumed when gate is in ideal/fixed state (0 or 1). (Leakage Current) Dynamic Power: The charge power consumed when gate is in switching state. (Short Circuit Current)
Q12> Macros are intellectual properties that you can use in your design. You do not need to design it. For example, memories, processor core, serdes, PLL etc. A macro can be hard or soft macro. A standard cell is a group of transistor and interconnect structures that provides a boolean logic function (e.g., AND,OR, inverters) or a storage function (flipflop or latch).
Q11> Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net.
Q10> Cell Delay is the amount of delay from input to output of a logic gate in a path. PT calculates the cell delay from delay tables provided in the technology library for the cell.
Q9> Sanity Checks mainly checks the quality of netlist in terms of timing. It also consists of checking the issues related to Library files, Timing constraints, IOs and Optimization Directives.
Q8> Aspect Ratio gives/ decide the shape of block. Aspect Ratio = Vertical Resources/ Horizontal Resources
Q7> Static Power: The charge power consumed when gate is in ideal/fixed state (0 or 1). (Leakage Current) Dynamic Power: The charge power consumed when gate is in switching state. (Short Circuit Current) Static power(SP) = Leakage current * supply voltage Leakage current = is (e ^qv/KT - 1) where is= reverse saturation current V = Diode voltage K = Boltzman constant T= Temperature Dynamic power consumption of CMOS circuitry is given by the formula: DP = C * V2 * f where P is the power, C is the effective switch capacitance, V is the supply voltage, and f is the frequency of operation. How to reduce dynamic power? 1) reduce power supply voltage Vdd 2) reduce voltage swing in all nodes 3) reduce the switching probabilty (transition factor) 4) reduce load capacitance
Q6> Floor planning control parameters are: Aspect Ratio & Core Utilization
Q5> Outputs of Floor Planning are: 1. Die/ Block Area 2. I/O pad placed 3. Macro placed
Q4> Inputs for floor planning stage are 1. Synthezed Netlist 2. SDC 3. Floorplanning control parametes 4. Physical partioningv information of design
Q3> Yes. For Sanity check purpose we need timing information.
Q2> 1. Minimize chip area 2. Making routing easy 3. Reduce IR drop across design
Q1> Floorplanning is process placing macros in chip/ core area.
Definition Clock Tree Synthesis (CTS) is a process which make sure that the clock gets distributed evenly to all sequential elements ...
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Definition Clock Tree Synthesis (CTS) is a process which make sure that the clock gets distributed evenly to all sequential elements ...
Can you please post answers ..
ReplyDeleteQ37> Set don’t use attribute on those library cells.
ReplyDeleteQ36> Power routes generally conduct a lot of current. In order to reduce effect of IR drop, we need to make these routes less resistive. Top metal layers are thicker and offer lesser resistance. This helps to reduce IR drop.
ReplyDeleteQ35> Following are the steps to be taken care while doing floor planning.
ReplyDelete1. Die Size Estimation
2. Pin/pad location
3. Hard macro placement
4. Placement and routing
5. Location and area of the soft macros and its pin locations
6. Number of power pads and its location
Q34>
ReplyDeleteThe distance between macro
= (no. of pins of macros*pitch*2)/no. of available routing layers
Metal pitch = Metal Width + Metal Space
the pitch varies for different metal layers. which metal layer pitch we need to consider? for e.g: in layerstack with 8 metal layers with 5 1x, 2 2x and 1 ultra thick metal, width and space is different for each of these categories.
DeleteIf macro pins include many metal, We should choose the pitch of TOP metal( For example, If macro have pin M4 and M6, We choose pitch of M6)
DeleteThis comment has been removed by the author.
ReplyDeleteQ33> Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs.
ReplyDeleteFollowing are the Process Advantages of Flip-Chip Design
1. Device Speed
2. Power and Ground Distribution
3. I/O Density with Area Array
4. Package Size /Form Factor
5. Low Stress over active Area
6. Reliability
Q32>
ReplyDelete1. No. of routing resources is increases.
2. To avoid crosstalk
3. To reduce RC value
Q31> Power Planning is used to distribute power to each part of design equally.
ReplyDeleteQ30> Inputs are
ReplyDelete1. Synthesized Netlist
2. SDC
3. Floor control parameters
4. Physical Partitioning information of design
Q29> Following are the congestion reduction techniques
ReplyDelete1. Placement Blockage
2. Module Constraints( Fence, Region, Guide)
3. Macro Padding ( Halos)
4. Cell Padding ( help to remove pin density)
5. Scan Chain Re-ordering
Q28>
ReplyDeleteYes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting unwanted buffers will also help in area recovery
Q27>
The main reason for using Sanity check is used to checking/qualifying the design for further acceptance at each stages of the physical implementation.
It qualifies the netlist in terms of timing, checks the issues related to library files, constraints files etc.
Following are the sanity checks carried out in physical design flow:
(a) check_library: It performs consistency checks between logical and physical libraries.
(b) check_timing: This is to check any unconstrained paths present in the design. check whether the pins/ports has it's corresponding I/O delays and also checks for the clock definition exists for all flop pins.
(c) check_design: This check is to report problems like undriven input ports, unloaded output ports, nets/ports with multiple drivers, unloaded nets, pins mismatch, cells or instances with out I/O pins/ports etc.
Q26>
ReplyDeleteFlip-chip assembly and wire bonding are the principal methods for interconnecting ICs.
Q24>
Core utilization = (standard cell area+ macro cells area)/ total core area
A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas 20% is left free for routing.
Q23>
Flylines means check net connections from macro to macro and macro to standard cells. If there is more connection from macro to macro, place those macros nearer to each other preferably nearer to core boundaries.
Q22>
In advanced Technology Nodes Macro Orientation is fixed since the Poly Orientation can’t vary, so there will be restrictions in Macro Orientation.
Q21>
Halo (Keep-out Region) is a region around boundary of fixed macro in desig in which no other macro or std cells can be placed. Placement of cells out of such region avoids congestion.
Q20>
ReplyDeleteIn order to avoid placement in some areas, they are used.
There are 3 types of Placement blockages
(a) Soft Blockage: allows only buffer & inverters to optimizes/ meet the timing. Used for Timing purpose only. Advantages is that Area is less, Timing is ease & less transition time.
(b) Hard Blockage: Won't allow any cell. Used for Routing purpose only. Advantages is used to avoid congestion. Disadvatages is Area is wastage.
(c) Partial Blockage: Some % of all celss can be used. No of available tracks can be increased uisng this. Advantages is to meet timing, routing easy & less IR drop.
Q19> Macro placement can be done using Macro guidelines.
1. Based on Flylines analysis (connections) between macros.
2. Macro should be near to core boundaries.
3. Communicating macros should be placed nearer.
4. Macro cell pin direction should be towards std cell direction.
5. Two Macros in between, we can placed/add soft bloackages
6. MAcros alignment should be follow
7. Criss Cross connection is not allowed.
8. Notches( edges) is avoided,
9. Orientation is not allowed.
Q18>
ReplyDeleteYes. Core is defined as the inner block, which contains the standard cells and macros. There is another outer block which covers the inner block. The I/O pins are placed on the outer block.
Q17>
1. Pad Limited Design :
A design is called Pad limited design when there are large number of pad cells determining the die size
2. Core Limited Design :
A design is called Core limited design when the large number of standard cells and macros determine the die size.
Q16>
Prerouting means routing of PG nets. Power Planning also called Pre-routing as the Power Network Synthesis (PNS) is done before actual signal (net) routing and clock routing.
For Area optimization, pre-routing is need to do it before placement(Flip Chip Concept)
Q15>
Total utilization T(F) of floorplan F is derived using the following equation
T(F) = (A(m) + A(p) + A(s) ) / A
where A(m) = Area occupied by macros,
A(p) = Area occupied by Pads/ Pad fillers
A(s) = Area occupied by Standard Cells
Q14>
ReplyDeleteCore Utilization = (Stdcell area + Macro Cell Area)/ ( Total Core Area)
Q13>
Yes.
Static Power: The charge power consumed when gate is in ideal/fixed state (0 or 1). (Leakage Current)
Dynamic Power: The charge power consumed when gate is in switching state. (Short Circuit Current)
Q12>
Macros are intellectual properties that you can use in your design. You do not need to design it. For example, memories, processor core, serdes, PLL etc. A macro can be hard or soft macro.
A standard cell is a group of transistor and interconnect structures that provides a boolean logic function (e.g., AND,OR, inverters) or a storage function (flipflop or latch).
Q11>
Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. This delay is caused by the parasitic capacitance of the interconnection between the two cells, combined with net resistance and the limited drive strength of the cell driving the net.
Q10>
Cell Delay is the amount of delay from input to output of a logic gate in a path. PT calculates the cell delay from delay tables provided in the technology library for the cell.
Q9>
Sanity Checks mainly checks the quality of netlist in terms of timing. It also consists of checking the issues related to Library files, Timing constraints, IOs and Optimization Directives.
Q8>
Aspect Ratio gives/ decide the shape of block.
Aspect Ratio = Vertical Resources/ Horizontal Resources
Q7>
Static Power: The charge power consumed when gate is in ideal/fixed state (0 or 1). (Leakage Current)
Dynamic Power: The charge power consumed when gate is in switching state. (Short Circuit Current)
Static power(SP) = Leakage current * supply voltage
Leakage current = is (e ^qv/KT - 1)
where is= reverse saturation current
V = Diode voltage
K = Boltzman constant
T= Temperature
Dynamic power consumption of CMOS circuitry is given by the formula:
DP = C * V2 * f
where P is the power, C is the effective switch capacitance, V is the supply voltage, and f is the frequency of operation.
How to reduce dynamic power?
1) reduce power supply voltage Vdd
2) reduce voltage swing in all nodes
3) reduce the switching probabilty (transition factor)
4) reduce load capacitance
Q6>
Floor planning control parameters are:
Aspect Ratio & Core Utilization
Q5>
Outputs of Floor Planning are:
1. Die/ Block Area
2. I/O pad placed
3. Macro placed
Q4>
Inputs for floor planning stage are
1. Synthezed Netlist
2. SDC
3. Floorplanning control parametes
4. Physical partioningv information of design
Q3>
Yes. For Sanity check purpose we need timing information.
Q2>
1. Minimize chip area
2. Making routing easy
3. Reduce IR drop across design
Q1>
Floorplanning is process placing macros in chip/ core area.
Does answer to ques 18 makes sense ? How macro can be placed between core and die area boundary ? Can you please elaborate ?
ReplyDelete