Static Timing Analysis Interview Questions

  1. What are the differences between static timing analysis and dynamic timing analysis?
  2. What is Setup time?
  3. What is Hold time?
  4. What is Setup time violation and Hold time violation?
  5. Why we are using timing constraints?
  6. What are synchronous and asynchronous resets?
  7. Explain Wire Delay Modeling for STA?
  8. How can you avoid Setup time violation?
  9. Draw the clock divide by 2 using D-flip flop. Explain the impact on duty cycle?
  10. What is the main objective of timing closure?
  11. What is delay cycle distortion and how to fix them?
  12. What are the inputs required for generating SPEF?
  13. What are virtual clocks and why they are used?
  14. What is On Chip Variation
  15. What is metastability?
  16. Define Latency? What are the different types?
  17. What is Clock Skew?
  18. Explain Positive Skew and Negative Skew?
  19. What is the difference between normal buffer and clock buffer?
  20. How the Jitter will effect on setup and hold analysis?
  21. What are the inputs required to run STA?
  22. What are the differences between OCV and AOCV
  23. What are the different types of timing analysis with merits and demerits?
  24. What is the difference between crosstalk and without crosstalk based STA analysis?
  25. What are the files required for crosstalk based STA analysis?
  26. What is the difference between PVT corners and RC corners?
  27. Is clock uncertainty reduced after clock tree synthesis? Justify.
  28. Explain the time borrow concept with Latch based design?
  29. What is PBA and explain?
  30. What is positive slack?
  31. What is negative slack?
  32. In physical design, which has more priority Setup violation or Hold violation?
  33. What is Slack?
  34. How can you avoid hold time violation?

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